1. Field
The following description relates to a source driver for use in a flat panel display (FPD) device, and more particularly, to a shift register circuit with improved operation characteristic, and a source driver for use in an FPD device, which includes the shift register circuit.
2. Description of Related Art
In general, an FPD device such as a TFT-LCD includes a flat panel display panel, a gate driver configured to drive gate lines of the flat panel display panel, and a source driver configured to drive source lines of the flat panel display panel.
As illustrated in FIG. 1, a conventional source driver includes a shift register circuit 100, a data register circuit 200, a hold register circuit 300, a level shifter circuit 400, a decoder circuit 500, and an output buffer circuit 600. The shift register circuit 100 is configured to generate latch clocks F_LAT1 to F_LATn to the data register circuit 200 according to a shift register clock signal SFT_CK so that RGB data to be displayed are sequentially stored therein.
The conventional shift register circuit 100 includes a plurality of shift registers S/R1 to S/Rn connected in series. Referring to FIG. 2, the shift registers S/R1 to S/Rn are configured to generate output signals SFT_OUT1 to SFT_OUTn by shifting a horizontal start signal STV at rising edges of the shift register clock SFT_CK during one horizontal sync clock HSYNC. Logic gates GA1 to GAn are configured to logically combine the output signals SFT_OUT1 to SFT_OUTn of the shift registers S/R1 to S/Rn and the shift register clock signal SFT_CK and provide the resulting signals to first latches of the data register circuit 200 as the latch clock signals F_LAT1 to F_LATn, and the first latches are configured to latch display data RGB. The hold register circuit 300 includes second latches configured to hold the display data RGB stored in the data register circuit 200 in response to a load signal SLAT.
In the conventional shift register circuit 100, since the shift registers S/R1 to S/Rn are implemented with only D flip-flops, the circuit size is small and the circuit configuration is simple. However, when the period of the shift register clock signal SFT_CK is short, a holding margin for the horizontal start signal STV is insufficient. In this case, since the shifting operation is not well performed, the shift registers S/R1 to S/Rn cannot normally generate the output signals SFT_OUT1 to SFT_OUTn. Consequently, the latch clock signals F_LAT1 to F_LATn cannot also be generated.
To solve these problems, a shift register circuit 100 of FIG. 3 was suggested. FIG. 3 illustrates only the shift registers S/R1 to S/Rn of the shift register circuit 100 of FIG. 1.
Referring to FIG. 3, the conventional shift register circuit 100 includes a plurality of shift registers S/R1 to S/Rn arranged in series. Each of the shift registers S/R1 to S/Rn is implemented with two flip-flops DF1 and DF2 connected in series. Referring to a waveform diagram of FIG. 4, the flip-flops DF1 provided at the front stage are configured to generate pulse signals SFT_P1 to SFT_Pn by shifting the horizontal start signal STV being input signals, or the output signals SFT_OUT1 to SFT_OUTn−1 of the previous shift registers S/R1 and S/Rn−1 at rising edges of the shift register clock signal SFT_CK. Meanwhile, the flip-flops DF2 provided at the rear stage are configured to generate the output signals SFT_OUT1 to SFT_OUTn−1 of the shift registers S/R1 to S/Rn−1 by shifting the pulse signals SFT_P1 to SFT_Pn−1 at falling edges of the shift register clock signal SFT_CK. A reset signal SFT_RSTB resets the flip-flops DF1 and DF2.
When assuming that the period of the shift register clock signal SFT_CK is Tck, the conventional shift register circuit 100 can ensure the holding margin more than Tck/2 with respect to the horizontal start signal STV, as compared with the case in which each shift register is implemented with a single flip-flop. Consequently, the shift register circuit 100 can operate more stably. However, since each shift register is implemented with two flip-flops, the circuit size increases.
In addition, referring to FIG. 5, when a signal STV_R generated by delaying the horizontal start signal STV by a delay time “td,stv” is applied to the input terminal D of the front flip-flop DF1 of the foremost shift register S/R1, and a signal SFT_CK_R generated by delaying the shift register clock signal SFT_CK by a delay time “td,ck” is applied to as the clock signal CK of the flip-flop DF1, the conventional shift register circuit 100 cannot perform the shifting operation if (td,ck)>(td,stv+Tck/2). That is, when Tck is small, the holding margin with respect to the horizontal start signal STV is still insufficient and thus the shift registers cannot normally generate the output signals.
Furthermore, since the shift register clock signal SFT_CK is continuously provided as the clock signal CK of the flip-flops DF1 and DF2 included in the shift registers having completed the shifting operation, the shift registers performing no shifting operation continuously latch the same data, causing unnecessary current consumption. In particular, since the shift register circuit 100 of the source driver shifts only one high level pulse, it serves as a fatal cause of unnecessary current consumption. Since only one of the shift registers constituting the shift register circuit 100 performs the shifting operation, current consumption is relatively large.